Processor modules have become popular in recent years as a means for providing reliable and efficient computer system upgrades. In a processor module, a processor is mounted to a circuit panel containing electrical interconnection paths, for example a printed circuit board, along with support electronics, for example random access memory (RAM) in the form of processor cache. Module electronics communicate with electronics mounted to a computer motherboard via an interface in the form of a high-speed connector. Ideally, as system clock rates increase, and processor functions evolve, the outdated processor module assembly can be removed from the motherboard at its connector and replaced by an upgraded module capable of operating at the higher rate, and/or with improved functionality.
Such a straightforward processor module replacement is not necessarily achieved by contemporary systems. When a module is inserted, the motherboard electronics may not necessarily recognize the new processor or support hardware employed by the replacement module. Conversely, the replacement processor may not recognize the system interface or xe2x80x9cchip setxe2x80x9d of the motherboard. In such a situation, the processor module may not operate to optimum efficiency, or worse, may not function at all.
The present invention is directed to an apparatus and method for a processor module/motherboard interface wherein a common interface is provided such that a common processor module is compatible with a variety of motherboard configurations in a manner that allows for the processor to be initialized regardless of the motherboard configuration. The present invention further allows for future generations of processor modules to be fully compatible with a common motherboard. In this manner, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards.
In one aspect, the present invention comprises a system for initializing a processor module connected to a motherboard. The processor module includes a processor; an initialization interface for receiving initialization commands for initializing the processor; a module information field, the module information field including status information pertaining to the processor module; and a first connector for transferring signals external to the processor module. The motherboard includes a second connector adapted to mate with the first connector for transferring signals between the motherboard and the processor module; a processor module information retrieval circuit for retrieving the module information field from the processor module through the first and second mating connectors; and an initialization command generator for generating initialization commands for the processor module based on the retrieved module information field, the processor receiving the initialization commands from the initialization interface through the first and second mating connectors.
In a preferred embodiment, the initialization interface comprises a serial interface, and the initialization commands comprise a serial bit stream. In an alternative embodiment, the initialization interface may comprise a parallel interface.
The processor module may further comprise a cache memory external to the processor and electronically coupled therewith. In this case, the module information field may include status information pertaining to the cache that is used for generating the processor initialization command. The initialization command may include commands for initializing the processor control registers, commands for initializing processor interfaces, or an initialization program to be operated by the processor to establish communication with the motherboard through the mating first and second connectors and for initializing hardware mounted to the motherboard.
The initialization command generator may comprise a control circuit for decoding data values stored in the, retrieved module information field; and a memory for storing a plurality of partial initialization sequences for a plurality of processors, the control circuit generating an initialization command from a subset of the initialization sequences based on the module information field. The memory may further include a programmable interface for updating the partial initialization sequences for updated processors. The partial initialization sequences may pertain to a plurality of processor types and processor clock rates.
The initialization command is preferably generated dynamically by the initialization command generator based on the retrieved module information field.
In another aspect, the present invention comprises a method for initializing a processor module connected to a motherboard. Status information pertaining to the processor module is stored in a module information field on the processor module. The motherboard retrieves the module information field from the processor module and generates initialization commands at the motherboard for the processor module based on the retrieved module information field. The initialization commands are transmitted to the processor module and used to initialize the processor module.